1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a high voltage device and a high voltage device for an electrostatic discharge protection circuit.
2. Description of the Related Art
At a high relative humidity (RH), people walking on a carpeted floor may accumulate sufficient electric charges to produce several hundreds to several thousand volts of static electricity. If the relative humidity is really low, static electricity of up to ten thousand volts may be produced. Furthermore, any machines used for packaging semiconductor devices or testing semiconductor devices may routinely produce several hundreds to several thousand volts of static electricity. When the charged body (for example, human body or machine) is in contact with a silicon wafer, static electricity will discharge through the wafer. The instantaneous power during the electrostatic discharge is capable of damaging the semiconductor devices within the wafer resulting in device failure. The same type of electrostatic discharge also threatens the integrity of any packaged chip.
A number of methods have been developed to protect semiconductor integrated circuit devices against possible damages due to an electrostatic discharge (ESD). The most common type of ESD protection is the incorporation of a special hardware inside the package. In other words, a specially designed electrostatic protection circuit is set up between an internal circuit to be protected and each bonding pad.
In U.S. Pat. No. 6,624,487, Kunz has disclosed a design having two N-type metal-oxide semiconductor (NMOS) transistors 100 and 102 (as shown in FIG. 1). As shown in FIG. 1, the gate of the transistors 100 and 102 are mutually connected. The drains 104a and 104b of these two transistors 100 and 102 are formed within N-type wells 106 and are connected together. Furthermore, one of the transistors (100 or 102) is used to switch on the parasitic bipolar transistor of the other transistor 102.
In another U.S. Pat. No. 6,365,941, Rhee of Samsung Electronics Co. Ltd. has disclosed an electrostatic discharge protection circuit (as shown in FIG. 2). As shown in FIG. 2, the electrostatic discharge protection circuit comprises a MOS transistor 200 and a Zener diode 202. The threshold voltage of the MOS transistor is higher than the operating voltage of the internal circuit but lower than the junction breakdown voltage of the drain of MOS transistors inside the internal circuit. Furthermore, a plurality of bonding pads may use a common diode having a large junction region instead of each bonding pad using a Zener diode.
In another U.S. Pat. No. 5,932,914, Horiguchi of NEC has disclosed an electrostatic breakdown protection device (as shown in FIG. 3). As shown in FIG. 3, the device comprises a protection diode 300, an NPN protection bipolar transistor 302, a P-type well 304, an N-type metal-oxide semiconductor field effect transistor (NMOSFET) 306 and an N-type buried layer 308. According to Horiguchi, during operating protective elements, the N-type buried layer absorbs electrons emitted by the protective elements so that the internal circuit is prevented from possible damage by the injected electrons.
In addition, in U.S. Pat. No. 6,365,932 (as shown in FIG. 4), Kouno et al of Denso also disclosed a power MOS transistor having protective diodes therein such that the power MOS has a larger breakdown differential voltage and a lower sheet resistance. As shown in FIG. 4, the power MOS is an up-drain type MOSFET. The MOSFET has a thicker gate dielectric layer on the drain side. Furthermore, a protective diode for surge bypassing is formed between the P-type doped region 400 and the deep N-type doped region 402.
Due to the demand for high voltage signals in recent years, processes capable of producing complimentary metal-oxide semiconductor (CMOS) transistors for high voltage systems have been developed. These types of transistors are often applied in high voltage power integrated circuits or video interface circuits including, for example, display driver ICs, power supplies, power managements, telecommunications, automobile electronics or industrial controls. To meet the demands of a high voltage system (for example, an operating voltage greater than 10V), the fabrication process of most MOS transistors adopt the following types of designs to increase the breakdown voltage. First, a less heavily doped epitaxial silicon layer is formed over the silicon substrate to rebuild the doping concentration of device region for increasing the breakdown and operating voltage. Second, more doped regions are added to the source or the drain of the MOS transistor so that the junction breakdown voltage is increased and with it the operating voltage. Third, a field oxide layer is disposed between the drain and the gate so that the breakdown voltage between the drain and the gate is increased.
FIG. 5 is a schematic cross-sectional view of a conventional symmetrical NMOS in a high voltage system. As shown in FIG. 5, the high voltage N-type well (HVNW) 500 and 502 are disposed underneath the source/drain N-type heavily doped regions 504 and 506. Furthermore, the N-type heavily doped region 504 and the high voltage N-type well 500 together form the source of the NMOS transistor while the N-type heavily doped region 506 and the high voltage N-type well 502 together form the drain of the NMOS transistor. Because the source and the drain are symmetrically disposed, the source and drain can be interchanged in circuit applications. In addition, the bulk region of the NMOS transistor is basically formed within the P-type well 508. The bulk potential is controlled through the P-type epitaxial silicon layer 510, the P-type substrate 512, the P-type well 514 and the P-type heavily doped region 516. Furthermore, various components of the NMOS transistor are fabricated on the thick P-type epitaxial silicon layer 510 (having a thickness of about 3˜20 μm) through conventional CMOS processes including, for example, ion implantation, thermal diffusion, oxidation and photolithography. In fact, the thin P-type epitaxial silicon layer 510 is the remaining portion of the thick epitaxial silicon layer after the CMOS processes. For the NMOS transistor in a high voltage system, the junction between the high voltage N-type well and the P-type well with high breakdown voltage constitutes the source/bulk interface. In addition, a field oxide isolation structure 518 is disposed between the drain and the polysilicon gate 520. Consequently, a high operating voltage can be applied to the drain or the gate of the NMOS transistor.
FIG. 6 is a schematic cross-sectional view of a conventional non-symmetrical NMOS transistor in a high voltage system. Unlike the structure in FIG. 5, a field oxide isolation structure 604 is disposed between the drain 600 and a gate 602 but no field oxide isolation structure 604 is disposed between the source 606 and the gate 602. Also, no the high voltage n type well 608 is disposed under the source 606. Since the source and the drain of the NMOS transistor are non-symmetrically disposed, the source and the drain cannot be used interchangeably in circuit design.
Although the aforementioned description always refers to an NMOS transistor, a PMOS transistor can similarly be built by changing the N-type/P-type doping. In addition, the aforementioned devices have good operating characteristics when applied to a high voltage system. However, these devices have a lower robustness due to a higher high breakdown voltage when applied in electrostatic discharge protection circuit. Moreover, the area needed to accommodate these devices is large.
FIG. 7 is a graph showing the characteristic current versus voltage (I-V) relationship of the symmetrical NMOS transistor in FIG. 5 measured by a transmission line pulsing (TLP) system. In general, the TLP I-V characteristic explains the state of operation of a device undergoing an electrostatic discharge. The I-V characteristic curve shows an increase in current with an increase in voltage starting at point A and reaches a maximum at the terminal point B (device failure). As shown in FIG. 7, the NMOS transistor only has a moderate electrostatic discharge protection capacity. When a pulse current passes through the NMOS transistor, the voltage is also raised so that there is a higher instantaneous power. The instantaneous power can damage the device irreversibly.